BASIC VFP Assembler 0.05

Version 0.05 of the BASIC VFP/SIMD assembler has been released for download

• Fixed VLDM/VSTM register list size

BASIC VFP Assembler 0.04

Version 0.04 of the BASIC VFP/SIMD assembler has been released for download

• Fixed VLDx/VSTx syntax error due to missing comma
• Fixed register type case-sensitivity
• Fixed listing missing final character
• Fixed optional 'ignored' data-type on data-processing instructions
• Fixed condition codes

Holiday Time

Things are a bit delayed at the moment as the holiday season takes over.   There has been some great feedback on the assembler and I hope to get another version out soon.   Like everyone else I'm away for quite a lot of August and also September, so it's slowing development right down.   We'll be back with an update as soon as there is something to report.

VFP Assembler 0.03

Another update to the VFP Assembler today with release 0.03.

* Fixed optional data-type variations - ARM p285
   (Note the use of multiple data-types is still not supported)
* Removed need to set sz in internal tables for F64/F32 variations)
* Fixed use of register lists in VTBL
* Other minor improvements to code and documentation

VFP Assembler Update

Shortly after 0.01 comes version 0.02 of the VFP/SIMD assembler with a number of bug fixes:

* Fixed VLDR/VSTR <reg>,<expr> not supported
* Fixed SP,LR,PC ARM register names
* Fixed user integer without R# prefix for ARM register numbers
* Other minor fixes
* Updates to documentation and release notes

Tested with the TestVFP script and a manual scan of output created by ObjAsm / DecAof

(Note the BASIC version in VFPLib supports the VLDR fix but not the ARM register names)

VFP assembler known bug list

Testing has thrown up some bugs that we are working on fixing:

* SP,PC,LR not supported as ARM core register names

* "R" prefix should be optional for an ARM core register, supporting existing syntax
   (We are verifying this doesn't cause other issues with similar pattern variations, leading to syntax errors)
   (The pattern table order will have to be updated to ensure bad-register errors occur at the correct time)

* LDR reg,<expr> not working due to missing pattern variation
   (<lbl> will be a new op name in the pattern tables to support an R15 based offset matching <#+-10>)

I suspect there will be more as there are a lot of (perfectly necessary) assembler directives that add complexity to the otherwise fairly simple syntax.

Using Functions within VFP/SIMD instructions

Having reviewed the documentation supplied with the 0.01 release, one thing that isn't clear is the way in which expressions are supported within the VFP/SIMD syntax.   This will be corrected in the next release.

Register Numbers
<type>#<expression>
Register numbers are a special case where the register type must be specified.   So where an ARM register can be simply specified as a number from 0-15, a Single/Double/Quad register must be prefixed by S,D or Q, and then a # followed by the expression.    For example Q#FNregister or D#(A%+B%)

Immediate constants
#<expression>
The same as for the standard ARM assembler, subject to encoding limitations as specified in ARM.   For a full 32bit or 64bit number, an 8bit constant can be shifted around and duplicated in 9 different ways.   For example #&FF, #&FF00, and #&FF00FF00  will encode for VMOV where as #&10F will not.

Immediate floating point or 64bit integers
#F32.<expression>
#F64.<expression>
#I64.<expression>
The special constructors take a number from 0-255 from <expression> and pass it through in raw form to the instruction encoding.   This is not particularly useful but completes the syntax.  We would recommend using other methods to define constants of these types.

Scalar Offsets
[<expression>]

Hopefully that helps to explain how things work.   Good luck to anyone who is testing the assembler and we look forward to some feedback in due course.