Tuesday, 12 July 2011

VFP Assembler 0.03

Another update to the VFP Assembler today with release 0.03.

* Fixed optional data-type variations - ARM p285
   (Note the use of multiple data-types is still not supported)
* Removed need to set sz in internal tables for F64/F32 variations)
* Fixed use of register lists in VTBL
* Other minor improvements to code and documentation

6 comments:

  1. ...some minor thinks I found will playing around:

    - You are not allowing to specify a data type for VAND, VORR, VEOR, may be also other bitwise instructions. Of course it makes no much sense to have data types, but as far as I see, other compilers and assemblers allow it and neglect the data type while assembling...so may be it would be good for compatibility.

    - In the syntax of VLDX (guessing also VSTX) you are not having a comma between the Dx registers and [Rx]. (So for example VLD1.8 D0 [R0] instead VLD1.8 D0,[R0]. Is that on purpose or just forgotten ?

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  2. Many thanks, I will get these sorted ASAP and have another look at ARM to try and get all the possible options.

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  3. Very useful upgrade to BASIC. Tried a few tests and found a few issues during testing.

    1. Lines are truncated one character short in the listing output.

    2. Condition code isn't accepted.

    3. Registers are not case insensitive.

    These can be corrected with the following changes in file s.vfp:

    1. R10 needs to hold the next character and AELINE needs to point one character further on after parsing is complete.

    After line 220 : LDRB R10,[AELINE],#1 ; read next character
    After line 222 : STR R10,[R13,#10*4] ; store new R10 value

    2. Need to skip over the condition code characters after processing.

    After line 591 : ADD AELINE,AELINE,#2 ; skip over condition code

    3. Convert initial character of register to upper case.

    After line 978 : VFP_UCase R0,R4 ; make upper case (use r4 as temp)

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